Current trends in the semiconductor and electronics industry require memory devices to be made smaller, faster and require less power consumption. One reason for these trends is that more personal devices are being manufactured that are relatively small and portable, thereby relying on battery power. In addition to being smaller and more portable, personal devices are also requiring increased memory and more computational power and speed. In light of all these trends, there is an ever increasing demand in the industry for smaller, faster, and lower power dissipation memory cells and transistors used to provide the core functionality of these memory devices.
Semiconductor memories can, for example, be characterized as volatile random access memories (RAMs) or nonvolatile read only memories (ROMs), where RAMs can either be static (SRAM) or dynamic (DRAM) differing mainly in the manner by which they store a state of a bit. The basic CMOS SRAM cell generally includes two n-type or n-channel (nMOS) pull-down or drive transistors and two p-type (pMOS) pull-up or load transistors in a cross-coupled inverter configuration, with two additional nMOS select or pass-gate transistors added to make up a standard double-sided or differential six-transistor memory cell (a DS 6T SRAM cell, a 6T SRAM cell, or simply a 6T cell). 5 transistor SRAM cells (5T) and 4 transistor SRAM cells (4T) are also known. Additionally, application specific SRAM cells can include an even greater number of transistors, such as 8T and 9T cells, for example, embodied as cells with read buffers or multiport cells.
FIG. 1 is schematic of a conventional differential SRAM 6T cell 100. As illustrated, the SRAM cell 100 comprises a data storage cell or latch 102, generally including a pair of cross-coupled inverters, for example, inverter 112, and inverter 114, the latch 102 operable to store a data bit state. Cell 100 also comprises a pair of wordline pass transistors 116, 118 to read and write the data bit between the cross-coupled inverters 112, 114 and bit lines BL 130, BL-bar 132, when enabled by wordline 134. Cell 100 is a symmetric cell since inverter 112 and inverter 114 are designed to be identical, as are the respective word line pass transistors 116, 118.
Respective inverters 112, 114 comprise a p-type MOS (PMOS) pull-up or load transistor Q1 120, Q2 122 and an n-type (NMOS) pull-down transistor Q3 124, Q4 126. Pass gates (e.g., transistors) Q5 116, Q6 118 are n-channel as well, which generally supply higher conductance as compared to p-channel transistors. Pass transistors 116, 118 are enabled by wordline 134 and accessed by bit lines 130, 132 to set or reset the SRAM latch 100. Inverters 112, 114 of the SRAM memory cell 100 are connected together to a Vdd drain power supply line 140 and a Vss source power supply line 150.
As dimensions are reduced to scale down devices, it becomes increasingly difficult to achieve a balance in the relative strengths (e.g. drive current capability) of the pass gate, drive, and load transistors over the desired range of temperature, bias conditions, and process variations, as well as achieving matched transistor characteristics. As a result, SRAM cells formed as such can be adversely affected by varying operating characteristics and may be unstable and may not be able to retain the desired bit state, during either or both the read or write operations. Conversely, the cell may be stable but not writeable.
Moreover, as transistor scaling trends continue, it becomes increasingly difficult to design an SRAM cell that has both adequate SNM, adequate Vtrip, and also can endure read and write operations over the desired operating range of temperature, bias conditions, and process variations. As known in the art, Vtrip is essentially a measure of the ability of a cell to be written into, and there is an interdependency between SNM and Vtrip in SRAM cell design. For example, if the pass gate is too strong relative to the drive transistor, SNM is degraded. If the pass gate is too weak relative to the load (pull-up) transistor, Vtrip is degraded. Also, if the load transistor is too weak relative to the drive transistor, SNM is degraded.
Therefore, whatever generally improves SNM, also degrades Vtrip, and vice versa. With technology scaling to the 45 nm node and beyond, it may no longer be possible to achieve a balance in the relative strengths of the pass gate, drive, and load transistors over the desired range of temperature and bias conditions as well as process variations. Thus, with the increasing random variation of transistor characteristics with scaling, it is increasingly difficult to design an SRAM cell.
Circuit designers have developed asymmetric SRAM cells (referred to herein as asymmetric conventional SRAM cells) in which one or more columns have higher threshold (or more generally lower transconductance) transistors connected to one bit line and lower threshold (or more generally higher transconductance) transistors connected to an opposing bit line. For example, transistors on a “slow” side of a given column may have a high threshold voltage and thus a lower read current but also a lower leakage to the bit line, and transistors on a “fast” side of the column may have a low threshold voltage and thus a larger read current but also a larger leakage current to the bit line. However, the conventional asymmetric SRAM cell does not help stability or ability to write. Accordingly, there is a need for an improved SRAM cell design that is compatible with technology scaling to the 45 nm node and beyond, and that largely overcomes the performance tradeoffs and provides good performance during all operating conditions for SNM, VTrip and IRead, and also minimizes power and die area.